Phase change memory stack with treated sidewalls

ABSTRACT

Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall

PRIORITY APPLICATION

This application is a continuation of U.S. application Ser. No.15/090,292, filed Apr. 4, 2016, which is a divisional of U.S.application Ser. No. 14/266,415, filed Apr. 30, 2014, now issued as U.S.Pat. No. 9,306,159, all of which are incorporated herein by reference intheir entireties.

BACKGROUND

Memory devices are typically provided as internal, semiconductor,integrated circuits in apparatuses such as computers or other electronicdevices. There are many different types of memory includingrandom-access memory (RAM), read only memory (ROM), dynamic randomaccess memory (DRAM), synchronous dynamic random access memory (SDRAM),and non-volatile (e.g., phase change memory, flash) memory.

Non-volatile memories are important elements of integrated circuits dueto their ability to maintain data absent a power supply. Phase changematerials have been investigated for use in non-volatile memory cells.Phase change memory (PCM) elements include phase change materials, suchas chalcogenide alloys, that are capable of stably transitioning betweenamorphous and crystalline phases. Each phase exhibits a particularresistance state and the resistance states distinguish the logic valuesof the memory element. Specifically, an amorphous state exhibits arelatively high resistance and a crystalline state exhibits a relativelylow resistance. One of different logic levels (e.g., logic 1 or logic 0)can be assigned to each of these states.

There are general needs to improve PCM devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a cross-sectional view of a typical phase changememory stack.

FIGS. 2-7 illustrate an embodiment of a process flow to fabricate aphase change memory stack having treated sidewalls.

FIG. 8 illustrates a block diagram of a memory system in accordance withthe embodiments of FIGS. 2-7.

FIG. 9 illustrates a plot of adhesion species deposition depth versuspulse voltage.

FIG. 10 illustrates a plot of adhesion species deposition depth versusimplant nominal dose.

DETAILED DESCRIPTION

As described subsequently, a method for fabricating a memory stack(e.g., memory device) with treated sidewalls can increase the adhesionof dielectric passivation material to the electrodes. This can reduceinter-diffusion between the electrodes and adjacent materials in thememory stack.

FIG. 1 illustrates a typical memory cell stack for a PCM. Carbon can beused as top 101, middle 102, and bottom 103 electrodes for the memorycell stack. Carbon is chemically inert and does not react easily withthe phase change material 110 or the selector device material 111. Thisinert chemistry can also lead to poor adhesion of sidewalls to thecarbon electrodes. As a result, it can be possible for the sidewallmaterial 120, 121 to inter-diffuse 130, 131 between the selector devicematerial 111 and the phase change material 110. This can occur at higherlocal temperatures during device operation. The inter-diffusion cancause reliability issues, degrade leakage current, and affect thresholdvoltage stability.

FIGS. 2-7 illustrate various steps in fabricating a memory stack (e.g.,PCM) in addition to treating the sidewalls of the memory stack with anadhesion species. These fabrication steps are for purposes ofillustration only as the different elements of the stack can be formedby different processes.

FIG. 2 illustrates an embodiment of a blanket deposition of the initialmemory stack material 200. The memory stack can include a word linematerial (e.g., tungsten (W)) 201. A first electrode material 202 (e.g.,carbon) can be formed on the word line material 201. A selector devicematerial 203 may be formed on the first electrode material 202.

The selector device material 203 (SD) may include Selenium (Se), Arsenic(As), Germanium (Ge), Tin (Sn), Tellurium (Te), Silicon (Si), Lead (Pb),Carbon (C), or Bismuth (Bi) as well as other materials. Otherembodiments can include selector device material 203 comprising one ormore of these elements as well as one or more of these elements combinedwith other elements.

A second electrode material 204 (e.g., carbon) can be formed on theselector device material 203. A phase change material 205 can be formedon the second electrode material 204.

The phase change material 205 (PM) can include chalcogenide elementssuchas Germanium (Ge), Antimony (Sb), Tellurium (Te), Indium (In) as well asother chalcogenide elements, combinations of these elements, orcombinations of these element with other elements. The phase changematerial 205 can additionally include Aluminum (Al), Gallium (Ga), Tin(Sn), Bismuth (Bi), Sulphur (S), Oxygen (O), Gold (Au), Palladium (Pd),Copper (Cu), Cobalt (Co), Silver (Ag), or Platinum (Pt) as well as otherelements. Additional embodiments can combine these elements with thechalcogenide elements.

A third electrode material 206 (e.g., carbon) can be formed on the phasechange material 205. Forming the third electrode material 206, as wellas the other materials 201-205 of the memory stack, can be done with ablanket deposition method or some other deposition method.

After the initial memory stack material 200 has been formed, an etchprocess (e.g., dry etch) can be performed on the stack material 200 tocreate trenches 301-304 as illustrated in FIG. 3. FIG. 3 illustratesthat the stack material 200 has been divided by the plurality oftrenches 301-304 into a plurality of memory stacks 311-315, each stackcomprising the architecture illustrated in FIG. 2.

In another embodiment, the stack material 200 can be dry etchedpatterned in both x and y directions. Thus, subsequent sidewall linerscan be added on four sidewalls, as illustrated in FIG. 7.

FIG. 4 illustrates the treatment of the sidewalls of particular ones ofthe stack 311-315 as formed in FIG. 3. This treatment enhances thedielectric liner adhesion to the electrode surfaces. In an embodiment, aplasma immersion technique (e.g., plasma doping) can be used to implantan adhesion species in the stack sidewalls and deposit a dielectricliner (e.g., nitride). While FIG. 4 illustrates the treatment processwith regard to only one sidewall of one electrode, the sidewalls of theother electrodes can experience a similar process.

The sidewall treatment process illustrated in FIG. 4 includes a step 430of implanting the sidewall of the carbon electrode(s) 204 with anadhesion species (e.g., boron) using a relatively low energy (e.g., <3keV) plasma doping (PLAD) process 400. This can be accomplished byexposing the sidewall to a diborane gas (B₂H₆) resulting in a B—C layer410 as a result of the boron terminating unsatisfied atomic bonds of thecarbon.

A subsequent step 431 includes depositing a boron film 411 on theelectrode 204. As a result of the PLAD implant/deposition process 400, agradient structure 420 of B—C bonds and the boron film is formed thatcan be approximately 1-6 nm thick.

Another step 432 includes implanting a dielectric material (e.g.,nitride (N)) into the B-C gradient 420. For example, a relatively lowenergy (e.g., 0-2k eV) NH₃ or N₂/H₂ PLAD process 401 can implantnitrogen atoms into the boron film 411 to form a BN_(x) film 412 on thecarbon electrode 204 sidewall. The BN_(x) film 412 can he referred to asthe sidewall liners or dielectric liners.

The process illustrated in FIG. 4 can sult in a dielectric liner 412that can be a few atomic layers thick. If a thicker BN_(x) film isdesired, the process of FIG. 4 can be repeated.

Relatively low energy plasma immersion implant can have advantages ifused in this process. For example, conformal doping can be used in theprocess in order to achieve a tunable implant/deposition operationregime and a shallow profile. The ion bomb bombardment nature of animplant process can enhance an adhesion-friendly species (e.g., boron)by intermixing with the electrode material. For example, the implantedboron can improve adhesion by species intermixing and terminatingunsatisfied atomic bonds (e.g., carbon bonds). Other adhesion speciesbesides boron that have similar properties can also be used. Thisprocess can he accomplished at approximately room temperature. To formthe PCM cells, electrically insulated pillars are formed (e.g., by dryetching) in the hit line direction while the memory stacks are formed inthe word line direction.

FIG. 5 illustrates the stacks 311-315 as a result of forming thesidewall liners 500-508 on the sidewalk of the stacks 311-315 as seen inFIG. 4. The process to form the sidewall liners 500-508 can use anydielectric material that can he implanted into the adhesive species film411. For purposes of illustration, a dielectric material like AlSiO, canbe used.

FIG. 6 illustrates an embodiment for forming a dielectric fill material601-604 between adjacent memory stacks. The dielectric fill material601-604 can electrically isolate each of the memory stacks. Thedielectric fill material 601-604 can he the same material as thesidewall liners 500-508 or a different dielectric material.

FIG. 7 illustrates an embodiment for forming additional decks of memorystacks. For example, FIG. 7 shows two memory stacks 701, 702 coupledtogether at a common bit line 703. The sidewalls or the sidewall linertreatment described previously with reference to FIG. 4 and below withreference to FIG. 8 may he repeated for the memory stacks at each of thedecks. Other embodiments can have additional decks of memory stacks 701,702. This embodiment can be obtained by a patterned dry etch process inboth the x-direction and the y-direction and the liner added to the farside sidewall.

The represented sequence of layers is for purposes of illustration only.Other embodiments can use other sequences. For example, the relativeposition of the PM and select material (SD) may be exchanged. Also, therelative positions of word line material and bit line material may bechanged (e.g., having hit lines at the bottom of the first deck and wordlines at the top of the first deck and possibly shared with a seconddeck stack.

FIG. 8 illustrates a block diagram of a memory system that include amemory device 801 that can use the memory stacks with treated sidewallsof FIGS. 2-7. A controller 800 may be used to control operations of thesystem. The memory device 801, coupled to the controller 800, mayinclude a memory array comprising memory cell stacks as described abovewith reference to FIGS. 2-7.

The controller 800 may be coupled to the memory device 801 over control,data, and address buses. In another embodiment, the address and databuses may share a common input/output (I/O) bus. The controller 800 canbe part of the same integrated circuit as the memory device 801 or asseparate integrated circuits.

FIG. 9 illustrates a plot of adhesion species (e.g., boron) depositiondepth (in nanometers) versus pulse voltage. This plot assumes a B₂H₆/H₂PLAD process. The plot shows that the boron deposition layer thicknesscan be increased at relatively low energy (e.g., <200 eV) and lowtemperature (e.g., <approximately 390° C.). Implant mode begins toincrease at approximately 200V.

FIG. 10 illustrates a plot of adhesion species (e.g., boron) depositiondepth (in nanometers) versus implant nominal dose (inatmospheres/centimeter). This plot shows that, even for higher energy(e.g., >3k eV), the implant/deposition intermixing mode can increase theadhesion species deposition thickness with dose.

As used herein, an apparatus may refer to, for example, circuitry, anintegrated circuit die, a memory device, a memory array, or a systemincluding such a circuit, die, device or array.

Conclusion

One or more embodiments of the method for memory stack sidewalltreatment can result in a memory device with memory stacks havingenhanced adhesion to the sidewall liners. For example, an adhesionspecies (e.g., boron) can intermix with particular materials of thememory stack to create better adhesion and, thus, reduced sidewallmaterial inter-diffusion. The adhesion species can be implanted in thesidewalls using a PLAD implant/deposition process to form a gradient ofboron film and an atomic intermixed structure of boron and carbon. Adielectric forming material :e.g., N) can then be implanted into thefilm to form a BN_(x) sidewall liner.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. Many adaptations willbe apparent to those of ordinary skill in the art. Accordingly, thisapplication is intended to cover any adaptations or variations.

What is claimed is:
 1. A method of fabricating a memory stack,comprising: forming the memory stack comprising multiple stackedelements, the memory stack defined in part by sidewalls; forming anadhesion species on at least one sidewall of the memory stack, includingintermixing the adhesion species with an element of the memory stack,and further including forming a film of the adhesion species on an outersurface of the intermixed adhesion species; and implanting a dielectricmaterial into the adhesion species film.
 2. The method of claim 1,wherein intermixing the adhesion species with the element comprisesimplanting the adhesion species into the sidewall of the element.
 3. Themethod of claim 2, wherein implanting the adhesion species into thesidewall of the element comprises performing a plasma doping process atan energy less than 3 keV.
 4. The method of claim 1, wherein implantingthe dielectric material into the adhesion species film comprises aplasma doping process at an energy within the range of 0-2 keV.
 5. Themethod of claim 1, wherein forming the adhesion species comprisesperforming both a plasma doping process and a deposition process.
 6. Themethod of claim 5, wherein performing the plasma doping processcomprises performing a plasma doping of boron into the sidewall of theelement of the memory stack.
 7. The method of claim 6, whereinimplanting the dielectric material into the film comprises implanting anitride forming material into the film to form a boron and nitride(BN_(x)) dielectric film.
 8. The method of claim 1, wherein forming thememory stack comprising forming multiple stacked elements comprising:forming a word line material; forming a first electrode material overthe word line material; forming a variable resistance material over thesecond electrode material; and firming a second electrode material overthe phase change material.
 9. The method of claim 8, wherein at east oneof the st and second electrode materials includes carbon.
 10. The methodof claim 9, wherein the boron adhesion species terminates unsatisfiedatomic bonds of the carbon.
 11. The method of claim 8, wherein formingthe word line material comprisesforming a material including tungsten.12. A memory structure, comprising: multiple memory stacks, each memorystack including, an electrode, a variable resistance material comprisinga chalcogenide material, the variable resistance material disposed to afirst side of the electrode in the memory stack, and wherein at leastthe electrode has a surface doped with an adhesion species thatintermixes with the material of the electrode, and a film comprising thematerial of the adhesion species formed over at least doped surface ofthe electrode.
 13. The memory device of claim 12, wherein electrodecomprises carbon, and wherein the adhesion species comprises boron. 14.The memory device of claim 12, further comprising a dielectric materialliner implanted into the adhesion species film.
 15. The memory device ofclaim 14, wherein the adhesion species comprises boron and the implanteddielectric material liner comprises boron and nitride (BN_(X)).
 16. Thememory device of claim 14, wherein the variable resistance materialcomprises one or more of Germanium (Ge), Antimony (Sb), Tellurium (Te),Indium (In), Aluminum (Al), Gallium (Ga), Tin (Sn), Bismuth (Bi),Sulphur (S), Oxygen (O), Gold (Au), Palladium (Pd), Copper (Cu), Cobalt(Co), Silver (Ag), and/or Platinum (Pt).
 17. A method for fabricating amemory device comprising: forming multiple memory stacks defined in partby sidewalls, each memory stack fabricated by: forming a first electrodeover a word line material; forming a variable resistance material overthe first electrode; forming a second electrode over the variableresistance material; and patterning and etching the first and secondelectrodes and the variable resistance material to form the multiplememory stacks; forming an adhesion species on at least one sidewall ofeach of multiple memory stacks using a doping process and a depositionprocess, wherein the adhesion species comprises a first portionimplanted to intermix with at least one element of the memory stack, anda second portion comprising a film of the adhesion species over thefirst portion; and forming a liner material on the sidewalls of multiplememory stacks by implanting a dielectric material into the film of theadhesion species.
 18. The method of claim 17, wherein forming theadhesion species comprises forming a gradient structured adhesionspecies on the sidewalls, comprising: using a plasma doping process toimplant a boron species; and using a deposition process to form a boronfilm on the sidewall over the implanted boron species.
 19. The method ofclaim 17, wherein ning the liner material comprises forming a boron andnitride (BN_(X)) liner iia over at least one of the first and secondelectrodes.
 20. The method of claim 17, further comprising forming adielectric fill material between pairs of the memory stacks.
 21. Themethod of claim 17, wherein forming the liner material comprises formingthe liner material through a plasma doping process at a temperature ofless than 390␣ C.